open_project spmv_ellpack
set_top ellpack
add_files spmv_ellpack.cpp
add_files -tb "spmv_ellpack_tb.cpp input.data check.data"
open_solution solution1
set_part xc7z010clg400-1
create_clock -period 10 -name default
csim_design
csynth_design
cosim_design
exit
